Typically, a computer system contains a processor, a bus, and other peripheral devices. The processor is responsible for executing instructions using the data in the computer system. The bus is used by the processor and the peripheral devices for transferring information between one another. The information on the bus usually includes data, address and control signals. The peripheral devices comprise storage devices, input/output (I/O) devices, etc.
Portable computers are common in the market today. These portable computers, often referred to as laptop and notebook computers, are often powered by batteries. Being that a battery only provides power for a specific duration (i.e., its battery life), efforts are currently being made to extend the battery life. In other words, for the same weight and performance of the computer system, efforts have been concentrated on maximizing the life of the computer system battery.
One method of extending the battery life is to reduce power consumption in the computer system. Power consumption may be reduced by powering up parts of a computer system only when they are required. In the prior art, there are many schemes for monitoring and controlling the consumption of power to a data processing device or devices when full operation is not desired or necessary. Many of them involve controlling the amount of power consumption of a memory unit. In at least one other system, described in U.S. Pat. No. 4,381,552, a "wait" signal is generated causing the processor to enter a standby mode. In the standby mode, power consumption is reduced. Often this is accomplished by stopping the processor clock since most of the power used is dynamic or switching power, and proportional to clock frequency. However, some processors contain dynamic cells internally, requiring constant clocking. Therefore, the stopping of a clock is not an option.
Another prior art technique for reducing power consumption in a computer system is U.S. Pat. No. 5,239,652 wherein the operating system running on a central processing unit (CPU) determines when the CPU is not actively processing and generates a signal that causes the CPU to be disconnected from the power supply. Periodically in response to pulses sent by a periodic timer or interrupts, the CPU is powered on, at which time the CPU performs any tasks that have arisen since the CPU has been powered off. Only interrupts or a periodic event is used to trigger the exit from the powered off state. It is only after exiting the powered off state that the computer system will be responsive to other types of operations, such as bus requests. However, it is desirable to allow other computer system operations to cause an exit from the powered off state. Also in this prior art technique, only the operating system running on this CPU is responsible for determining when to be powered down. Therefore, the CPU may only be powered off from the CPU sub-system of the computer system. It may be desirable to turn off the processor from the input/output (I/O) portion of the computer system, in the case of, for example, an alternate processor operating as a "master" in the system.
Many of the prior art power down techniques do not permit exiting the power down sequence once it has been initiated. That is, once the sequence of events to power down a device or computer system has begun, it must be completed before returning to full power. This may result in a large latency between handling interrupts. Thus, it may be desirable to abort the power down of a device or computer system prior to entering the powered down state to reduce interrupt servicing latency.
By disabling the power to the CPU, the CPU may still be receiving clocking signals. Driving the clocks while the CPU is in the powered off state could cause damage to the CPU. Thus, it is desirable to stop clocking of the integrated circuit when the integrated circuit is to be powered down.
Many mechanisms exist in the prior art to provide clocking signals. For instance, phase-locked loops (PLLs) have been used to provide clocking signals. A PLL produces clock signals in accordance with a reference clock signal. The PLL becomes synchronized, or "locked" to the reference clock signal after a period of time. The PLL must attain lock every time upon powering up. If clock signals are turned off by turning off a PLL, the time required to power up can be no shorter than the time to attain lock again. Such a time period may appear to be too long and impact the responsiveness of a computer system. However, if an integrated circuit needs to be clocked by a PLL device due to strict or fast timing requirements, stopping and starting the clock may add intolerable latencies to responsiveness. Thus, if the clock signals are not going to be received by the integrated circuit during some period of time, then it should be done such that the time from enabling the clocks to providing valid clock signals is minimized.
The present invention provides for powering down a processor that is clocked by an external PLL clock source. In addition, in the present invention, events other than interrupts can cause the processor to exit the powered down state. Also the present invention provides for controlling the powering down of a processor from both sides of a computer system: the I/O portion or expansion side and the processor subsystem side. The present invention provides a power down bypass or abort method for late arriving interrupts to reduce interrupt servicing latencies. The present invention also provides an alternate method of powering down the processor as well as powering down other parts of the system to serve a low power "sleep" mode. The present invention also provides for disabling the clocks to the processor, without incurring a delay in the PLL achieving lock when re-enabling the clocks to the processor (power-up).